Physical Design Engineer(Onsite)
First preference : SAN JOSE, CA
Expected Start Date: 1st week of June
Interview:Phone+Skype
Job Description:
Mandatory Skills/Experience
Experience in leading and executing Full-chip Hierarchical Physical Design of Mixed-signal chips.
Experience in understanding and writing synthesis design constraints for hierarchical physical partitions
Experience in STA and Timing closure for very high-speed designs >1 GHz
Experience with TSMC 12FFC node and other FINFET nodes (desirable)
Experience with Synopsys ICC2 based P&R flow
Himanshu Goswami
Sr. IT Technical Recruiter
Stellent IT Phone : 3217856032
Email: Himanshu.goswami @stellentit.com
Gtalk: Himanshu.goswami om
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